A double data rate type three (DDR3) synchronous dynamic random access memory (SDRAM) is now a most widely applied memory product, and has huge advantages on costs, bandwidth, power consumption, and the like.
A DDR3 SDRAM generally uses burst access with a length of eight, and one time of burst access refers to one read (RD) or write (WR) command for a memory. For example, if a data bit width of a DDR3 chip is 16 bits and a burst length is eight, where the data bit width herein refers to a total width of a data line between a processor and the DDR3 chip and the burst length refers to a length of data accessed in one time of burst access, 16 bit×8=128 bit data is returned by each time of reading.
A DDR3 SDRAM memory body generally includes eight different banks (Bank), each Bank is divided into multiple rows, each row is called a page (Page), and each page is further divided into multiple columns. As shown in FIG. 1, a typical reading process is: a processor sends, to a DDR3 SDRAM, an activation (ACT) command, and a Bank address (the Bank address is identified by BA0 in the figure) and a row address (such as RAx and RAy in the figure) that are to be accessed, to open a page, and then sends a RD command and an in-page column address (such as CAx in the figure); and read operations may be performed continuously within one page by using read commands, but in an inter-page case, it is necessary to send a precharge (PRE) command first to close a currently opened page and send an ACT command again to open a corresponding page. In this way, when switching is performed between pages in a same Bank, a latency of tRTP+tRP+1 clock cycles is needed between two read commands, where, tRTP is a time from sending a read command to sending a precharge PRE command (that is, a close Bank command), tRP is a time needed for closing a Bank, and at least one clock cycle is needed from sending an ACT command to sending a read command. As shown in FIG. 2, a typical writing process is: a processor sends, to a DDR3 SDRAM, an ACT command, and a Bank address and a row address that are to be written into; and write operations may be performed continuously within one page by using write commands, but in an inter-page case, it is necessary to send a PRE command first to close a currently opened page and send an ACT command again. In this way, when switching is performed between pages in a same Bank, postponing of WL+4+tWR+tRP clock cycles is needed between two WR commands, where WL is a time of a write latency, that is, after a write command is sent, WL clock cycles still need to elapse before a write operation is started, afterwards, there is a write time of four clock cycles, tWR is a write recovery time after the write operation is performed, and tRP is a time for closing a Bank.
It may be seen from the foregoing process that when two contiguous memory access operations access different pages of a same Bank, after an access operation is performed, a relatively long latency is needed before a later access operation is performed, which severely reduces access efficiency.